In order to follow the constant evolution of the microelectronics industry aiming at a significant reduction in the dimensions of the devices, a three-dimensional (3D) integration method has been adopted. In addition to enabling a significant increase in the circuit performances and a reduction in the power consumption thereof, 3D integration makes it possible to reduce the production costs too. This is true provided sufficiently mature and technologically strong 3D methods exist.
The application of the present invention relates to a 3D integration having a high density of interconnections. A 3D integration method may be broken down into three distinct parts: a first part corresponding to the production of conducting elements or through vias (or TSV, for <<Through-Silicon Vias>> or <<TGV>> for <<Through-Glass Vias>>), a second part corresponding to the production of the interconnections, and eventually a third part corresponding to die bonding.
The present invention mainly relates to the production of interconnection pads. Advantageously, wafers comprising a substrate, specifically made of silicon, whereon the devices have been executed with a technology of the <<vias first>> or <<vias middle>> type are used. In the so-called <<vias middle>> technology, the vias conducting elements have very small dimensions, which makes it possible to address applications requiring a higher density of interconnections. The <<vias first>> technology, still under development, will provide, in the longer run, greater possibilities of integration, and may be adapted to very high applicative constraints (reinforced insulations, high voltages).
The <<rear face>> technology further executed on these wafers starts, for example, with a temporary sticking on a silicon or glass substrate, or any other technique making it possible to thin the rear face of the wafers with vias conducting elements. The thinning of the wafers with vias conducting elements is conventionally executed by polishing or rectification (<<grinding>>), followed by a step of releasing the constraints for example by chemical-mechanical polishing (CMP). The step of <<grinding>> thus consists in thinning the wafers with vias conducting elements from the rear face and stops a few microns above the rear of the vias conducting elements (the rear of the vias conducting elements is also called <<copper nails>>). The reveal of the rear of the conducting elements or <<via reveal>> may be executed by mechanical-chemical polishing. However, other techniques exist such as the Reactive-Ion Etching (RIE) or still chemical etching based on tetramethylammonium hydroxide (TMAH) or still a mixture based on hydrofluoric acid and nitric acid (HF/HNO3), for example. The step of <<via reveal>> is executed by etching based on sulphur hexafluoride (SF6), followed by the deposition of a dielectric layer making it possible to insulate the future interconnections from the silicon substrate. It may be a mineral dielectric selected among silicon dioxide (SiO2) or silicon nitride (SiN), which may be deposited by Chemical Vapor Deposition (CVD) or a dielectric resin (<<spin-on>> method). The reveal of the vias conducting elements is then executed by chemical-mechanical polishing. Eventually, the last step consists in executing interconnections called micro-pillars.
The technological steps used to execute such interconnections are first the deposition of a bonding layer or barrier layer, then a second metallic layer having a lower resistivity, or a bilayer based on, for example titanium and copper. A step of lithography used to define the interconnection zones (spreading then development of the resin) is executed next. Then, electrolytic growth of the interconnection pad (made of copper or nickel, for example) is executed. Then, the resin is <<stripped>>. The method ends with etching of the barrier layer, then the metallic layer having a lower resistivity by chemical etching, for example.
Rear face integration is disclosed in the article by P. Coudrain and al., entitled: <<Towards Efficient and Reliable 300 mm 3D Technology for Wide I/O Interconnects>>, published in the <<Proceedings of the Electronics Packaging Technology Conference (EPTC)>>, pp. 335-340, Dec. 5-7, 2012, Singapore.
In the method described above, a step of lithography is executed to define the interconnection zones above TSV conducting elements. Alignment is carried out visually on the TSV conducting elements, for a critical dimension of a few microns.
The drawback of this approach lies in the alignment constraints, during a step of lithography, on micrometric or even nanometric devices. Such inaccuracy in the alignment results both from the technique specific to the positioning of the mask, and also from thermal dilatation effects (different dilatation coefficients between the mask and the silicon substrate).
The step of lithography may also come with compatibility problems between the resin and the electrolytic baths. Such incompatibilities may cause detachment of the resin or modifications in the slope of the resin, resulting in infiltrations into the baths during an Electro-Chemical Deposition (ECD), or adherence problems.
This technique is valid for the present dimensions of TSV which have a diameter of approximately 10 micrometers (micrometer or micron=10−6 meter).
Besides, in order to meet the needs relative to devices the dimensions of which are always smaller, finer lithography techniques should be considered. This would be a major change for <<rear face>> integration since the latter would require creating a totally new alignment strategy.
An additional drawback is the multiplicity of associated technological and control steps (spreading of the resin, first annealing, insulation, development, second annealing, stripping the resin, etc.) required by a step of lithography.
The present invention makes it possible to solve all or at least a part of the drawbacks of the present techniques.